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Andes NX27V in Microprocessor Report May 25th Issue:  
"Andes Plots RISC-V Vector Heading

In his MPR article, analyst Mike Demler describes the NX27V as a vector processor whose scalar unit is enhanced from the 5-stage Andes NX25 scalar core. He states that the configurable Vector Processing Unit (VPU) of the NX27V supports 128-, 256-, and 512-bit SIMD operations per vector instructions. The NX27V also implements the RISC-V RV64 scalar ISA, and Andes extensions. For a copy of the MPR article click here.

 

Visitors Worldwide Attended Andes
Successful Virtual RISC-V Con  


Starting on March 12, continuing every two weeks thereafter until May 21, and concluding on July 7 Andes produced an hour-long webinar in English and Chinese. The March 12th Webinar (Chinese) introduced Andes RISC-V V5 CPU product line; The March 26th (Chinese) broadcast featured Software Solutions for RISC-V. On April 9th (Chinese) the webinar introduced Andes Custom Extension™ (ACE) and demonstrated how it could be used to accelerate a domain-specific architecture. The April 23rd (Chinese) broadcast detailed how using ACE to enhance a RISC-V D25 core could produce a power-efficient, low-cost, compute-efficient TWS (True Wireless Stereo) solution. The May 7th (Chinese) webinar detailed Andes High Memory Efficiency 27 Series and Superscalar 45 Series CPU IP Cores. On May 21st, (Chinese) the broadcast described the NX27V, the first commercial RISC-V CPU core with Vector Extension. The concluding webinar on July 9th (Chinese) detailed how Andes Infuses high-efficiency and high-flexibility processor IP into artificial intelligence. It also included a description of Andes' NN software development kit for AI. 
Andes in EETimes: "Domain Specific Accelerators Will Drive Vector Processing on RISC-V"

In his EETimes article "Domain Specific Accelerators Will Drive Vector Processing on RISC-V" Board of Directors’ Advisor for Andes Technology, Charlie Cheng, stated:  "In the past 15 months, we have seen a great deal of demand for high performance with the addition of a powerful RISC-V vector extension, matching it with a high-bandwidth memory subsystem, and bringing the accelerator closer to the CPU. This is the type of computing requirement we believe will drive the demand for RISC-V and vector processing."  For the complete article click here.
IAR Systems and Andes Technology Will Support RISC-V P Extension for Packed-SIMD Instructions

On June 5, EEJournal, published the news that IAR Systems and Andes Technology Launched Support for the RISC-V P Extension for Packed-SIMD Instructions. Commenting on the news Dr. Chuanhua Chang, the Chair of RISC-V P extension Task Group and Head of Architecture Division of Andes Technology Corporation stated. “We are excited to partner with IAR Systems to further accelerate the performance of applications based on RISC-V in general and P extension in particular. We have achieved around 9x performance boost of CIFAR-10 inference with RISC-V P extensions. Packed-SIMD provides edge processors more computing power with higher energy efficiency and minimal increase in cost, and such capability empowers edge devices to deal with voice and slow video processing.  Together, we provide powerful solutions that will enable our customers to meet and exceed their project requirements.”
Andes, Imperas, & UltraSoC Team up for RISC-V
AI Inferencing/Machine Learning design Webinar

Andes, Imperas, and UltraSoC teamed up on a webinar detailing how their combined EDA, IP and debug tools could facilitate AI inferencing and machine learning designs using the open RISC-V CPU. Hosted by Quantum Leap Sales Founder, Mike Ingster, Kevin McDermott Imperas VP of Marketing presented "RISC-V & SoC Architecture Exploration for AI & ML Many-Core Compute Array"; Charlie Cheng, Board of Directors’ Advisor for Andes Technology, presented "Where RISC-V Sees Momentum: An Overview of Real-Time, Performance Opportunity"; and Gajinder Panesar, CTO of UltraSoC presented "It's All About the System." For a recording of the webinar click here.

Andes RISC-V Pavilion Presentations at Virtual DAC 2020
Drew a Large Audience


Over 500 visitors attended the on-line presentations in the RISC-V Pavilion at the virtual Design Automation Conference on Tuesday, July 21st. Andes Technology's Director of Field Applications Engineering for the U.S. John Min's Pavilion presentation, "Building a High Powered AI/ML accelerator using a RISC-V CPU core with Vector Extension" was particularly well attended. In case you were not able to view the presentation on the day of the event, it is still available to everyone on the virtual DAC 2020 website at this link.
TSMC customers, be sure to attend their biggest and, for the first time virtual, North American event TSMC Open Innovation Platform Ecosystem Forum on August 25th. Andes Technology's Director of Field Applications Engineering for the U.S. John Min will present "RISC-V & SoC Architecture Exploration for AI & ML Many-core Compute Arrays." Register now.
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