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Renesas Selects Andes RISC-V 32-Bit CPU Cores for Its First RISC-V Implementation of ASSP/MCUs

On October 1, Renesas announced that it had selected the AndesCore™ IP 32-bit RISC-V CPU cores to embed into its new application-specific standard products that will begin customer sampling in the second half of 2021. President of Andes Technology Corp. Frankwell Lin commented. “Renesas and Andes share the same vision to welcome the era of RISC-V being the mainstream CPU instruction set architecture (ISA) for system-on-chips (SoC). Not only does this represent a milestone for Andes, but it marks the arrival of the open-source RISC-V ISA as a mainstream computing engine. Renesas customers will benefit from a modern ISA constructed for the needs of 21st-Century computing.”
Learn the Latest on RISC-V and Vector Processing at All Six Andes Technology Corporation’s Presentations at the 2020 RISC-V Summit
Andes Technology Corporation will make six presentations at the virtual RISC-V Summit from December 8 to 10, 2020. Andes CTO and Executive VP, Charlie Hong-Men Su, will give an overview and update on "Andes RISC-V Processor IP Solutions." Andes Senior Director of Architecture Div., Chuan-Hua Chang, will present "AndesClarity: a Performance & Bottleneck Analyzer for RISC-V Vector Processors." Paul Ku, Deputy Technical Director of Architecture Div., will introduce "Building a Secure Platform with the Enhanced IOPMP."

Additionally, Deputy Software Manager, Shao-Chung Wang, will present "Extending Multicore Programming Framework for Vector Extension." Ding-Kai Huang, VLSI Manager, will discuss "Enhancing Verification Coverage for RISC-V Vector Extension Using RISCV-DV," co-authored with Tao Liu from Google. Andes Principal Architect, Thang Tran, will hold a 3-hour master class entitled "RISC-V Vector Extension Demystified."
Telink and Andes Announce the TLSR9 SoC with RISC-V Processor

Telink Semiconductor and Andes Technology have collaborated on a cutting-edge system on a chip for high-performance IoT applications. The Telink Semiconductor TLSR9 SoC features the D25F RISC-V processor and is the world’s first SoC that adopts a RISC-V DSP/SIMD P-extension, which is ideal for a variety of mainstream audio, wearables, and IoT development needs.  By supporting the RISC-V P-extension (RVP), the D25F significantly increases efficiency for small-volume data computation and makes compact AI/ML applications possible on edge devices. Tests have shown that the D25F can increase the speed at which CIFAR-10 AI models (a common type of image classification model) are run by a factor of 14.3 and increase the speed of keyword-spotting technologies by a factor of 8.9.
Picocom Embeds 32 Andes N25F RISC-V Cores into Its 5G NR Small Cell Baseband SoC
Picocom has selected the AndesCore N25F RISC-V 32-bit core integrated with the AE350 peripherals platform for its forthcoming 5G small cell distributed unit (DU) System-on-Chip (SoC). Picocom is a 5G open RAN baseband semiconductor company with vast experience in the field of small cells. Its chosen partner, Andes Technology, is a leading supplier of high-performance, low-power compact 32/64-bit RISC-V CPU cores and the Founding Premier member of the RISC-V International Association.

“We are delighted that Picocom recognizes the strength of N25F and utilizes dozens of them in clusters, along with the integrated Platform AE350 to design its advanced 5G small cell SoC.” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “It again validates that Andes’ RISC-V solutions are ideal to tackle the demanding requirements of high-speed protocol control with significant performance for applications such as storage, networking, and wireless communication.”

Andes Principal Engineer, Thang Tran, Presents at
Linley Fall Processor Forum

On Wednesday, October 21, 2020, during the Linley Fall Processor Conference, Andes Technology Principal Engineer, Thang Tran, presented "A RISC-V Out-of-Order Vector Processor." Here is an abstract of his talk: "The NX27V vector processor has 9 functional units and integrates the scalar FPU. Fourteen vector instructions can be concurrently executed. Innovative design algorithms are used to issue 8 micro-ops per cycle and allow vector instructions to be chained, executed, and completed out-of-order without the use of any temporary registers. This CPU IP can sustain performance of 96 GFLOPS, yet it was designed from start to final delivery in just 9 months by a small design and verification team." If you attended the conference, you can access the proceedings here.

Taking the Mystery out of Custom Extensions in
RISC-V SoC Design

In designing a system for many products today, power consumption, performance and die area constrain a lot of the complex artificial (AI) and machine learning (ML) SoC requirements. Extending the open-source RISC-V instruction set architecture (ISA) is often overlooked as an effective means to address these constraints. A recent webinar panel led by Quantum Leap Solutions, a design services company for the semiconductor industry, attempted to help take the mystery out of extending the RISC-V ISA for SoC designs. The webinar entitled "RISC-V Flexibility - The Power of Custom Extensions," fielded questions from over 100 attendees. Check out the panelists' insight.
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